3GPP Work Item mapping to Change Requests
3GPP Work Item = 1228 (LCRTDD-IubIur)
This page lists the approved Change Requests to 3GPP Technical Specifications and Reports associated with the above work item. Click on the CR find it in the CR table associated with the spec to which it pertains. Click on the spec to open its web page.
| Spec | CR number and Revision | CR Title |
|---|---|---|
| 25.401 | 0023 rev 1 | The impacts on TS 25.401 for supporting low chip rate TDD |
| 25.401 | 0033 | Uplink power control for LTDD |
| 25.401 | 0034 | Uplink power control for LTDD |
| 25.402 | 0014 rev 3 | The impacts on TS 25.402 for supporting low chip rate TDD |
| 25.402 | 0022 | Correction on TDD Radio Interface Synchronistion |
| 25.423 | 0309 rev 2 | The impacts on TS 25.423 for supporting low chip rate TDD in RNSAP |
| 25.423 | 0391 rev 2 | Alignment of LTDD to the latest R99 modifications |
| 25.423 | 0393 rev 1 | Uplink power control for 1.28 Mcps TDD |
| 25.423 | 0415 | Clarification on the reference of the “Neighbouring TDD Cell Information LCR” |
| 25.423 | 0423 | Support of 8PSK modulation for LTDD |
| 25.423 | 0487 | Cell Parameter ID IE definition for 1.28Mcps TDD |
| 25.423 | 0706 rev 2 | Uplink Synchronisation in 1.28Mcps TDD |
| 25.423 | 0707 rev 2 | Uplink Synchronisation in 1.28Mcps TDD |
| 25.423 | 0723 | Add UL SIR_target for Unsynchronized RL Reconfiguration in 1.28Mcps TDD |
| 25.423 | 0724 | Add UL SIR_target for Unsynchronized RL Reconfiguration in 1.28Mcps TDD |
| 25.423 | 0725 | Correction to RX Timing Deviation Lvalue range |
| 25.423 | 0726 | Correction to RX Timing Deviation Lvalue range |
| 25.423 | 0727 rev 2 | Slot Format for 1.28Mcps TDD |
| 25.423 | 0728 rev 2 | Slot Format for 1.28Mcps TDD |
| 25.423 | 0791 | Midamble Configuration for Midamble Shift LCR |
| 25.423 | 0792 | Midamble Configuration for Midamble Shift LCR |
| 25.423 | 0797 rev 2 | Uplink Timing Advance Control Parameters in LTDD |
| 25.423 | 0798 rev 2 | Uplink Timing Advance Control Parameters in LTDD |
| 25.425 | 0023 rev 4 | The impacts on TS 25.425 for supporting low chip rate TDD |
| 25.425 | 0030 | Correction on RACH data frame in Iur interface |
| 25.427 | 0042 rev 2 | The impacts on TS 25.427 for supporting low chip rate TDD |
| 25.427 | 0047 | Identify some parameter only used in 3.84Mcps TDD |
| 25.427 | 0057 | Uplink power control for LTDD |
| 25.430 | 0014 rev 2 | The impacts on TS 25.430 for supporting low chip rate TDD |
| 25.433 | 0358 rev 2 | The impacts on TS 25.433 for supporting low chip rate TDD in the NBAP Common Procedures |
| 25.433 | 0359 rev 3 | The impacts on TS 25.433 for supporting low chip rate TDD in the NBAP Dedicated Procedures |
| 25.433 | 0450 rev 2 | Alignment of LTDD to the latest R99 modifications |
| 25.433 | 0451 rev 1 | Corrections to TDD 1.28 Mcps RACH parameters |
| 25.433 | 0452 rev 2 | Uplink power control for 1.28 Mcps TDD |
| 25.433 | 0454 rev 1 | Removal of the timeslot in the Cell Setup Request TDD message for LTDD |
| 25.433 | 0470 | Support of 8PSK modulation for LTDD |
| 25.433 | 0547 | Cell Parameter ID IE definition for 1.28Mcps TDD |
| 25.433 | 0728 rev 2 | Uplink Synchronisation in 1.28Mcps TDD |
| 25.433 | 0729 rev 2 | Uplink Synchronisation in 1.28Mcps TDD |
| 25.433 | 0732 rev 2 | Modification of PICH Parameters LTDD |
| 25.433 | 0733 rev 2 | Modification of PICH Parameters LTDD |
| 25.433 | 0748 | Add UL SIR_target for Unsynchronized RL Reconfiguration in 1.28Mcps TDD |
| 25.433 | 0749 | Add UL SIR_target for Unsynchronized RL Reconfiguration in 1.28Mcps TDD |
| 25.433 | 0750 | Correction to RX Timing Deviation Lvalue range |
| 25.433 | 0751 | Correction to RX Timing Deviation Lvalue range |
| 25.433 | 0752 rev 2 | Slot Format for 1.28Mcps TDD |
| 25.433 | 0753 rev 2 | Slot Format for 1.28Mcps TDD |
| 25.433 | 0754 | SYNC_DL Code ID for 1.28Mcps TDD |
| 25.433 | 0755 | SYNC_DL Code ID for 1.28Mcps TDD |
| 25.433 | 0779 | Clarification to RACH for 1.28Mcps TDD |
| 25.433 | 0780 | Clarification to RACH for 1.28Mcps TDD |
| 25.433 | 0810 | Midamble Configuration for Midamble Shift LCR |
| 25.433 | 0811 | Midamble Configuration for Midamble Shift LCR |
| 25.433 | 0822 | Correction of PRACH Midamble for 1.28Mcps TDD |
| 25.433 | 0823 | Correction of PRACH Midamble for 1.28Mcps TDD |
| 25.433 | 0912 | Correction of the repetition name for 1.28Mcps TDD in the RADIO LINK RECONFIGURATION PREPARE TDD message |
| 25.433 | 0913 | Correction of the repetition name for 1.28Mcps TDD in the RADIO LINK RECONFIGURATION PREPARE TDD message |
| 25.433 | 0918 | ASN.1 corrections for 1.28Mcps TDD |
| 25.433 | 0919 | ASN.1 corrections for 1.28Mcps TDD |
| 25.435 | 0037 rev 3 | The impacts on TS 25.435 for supporting low chip rate TDD |
| 25.435 | 0042 | Identify some parameter only used in 3.84Mcps TDD |
| 25.435 | 0048 rev 1 | Uplink power control for LTDD |
| 25.435 | 0049 | Correction on RACH data frame in Iub interface |
| 25.435 | 0059 rev 1 | Uplink Power Control for TDD |
| 25.435 | 0085 | Correction on Paging Indication bitmap |
| 25.435 | 0086 | Correction on Paging Indication bitmap |
| 25.937 | 0001 | Rel4 correction on modulation type in LTDD |
page generated from database: 2024-11-04 08:42:08